1. Field of the Invention
The invention relates to the use of low dielectric constant (xcexa) materials for device fabrication, in particular ultra-large scale integration (ULSI) devices.
2. Discussion of the Related Art
For semiconductor devices, packing densities quadruple, and minimum circuit dimensions shrink by 70%, about every three years. The design rules for such packing density and circuit dimension require an increase in the number of metal interconnect levels and the reduction of metal pitch (i.e., the linewidth and spacing between adjacent metal lines). However, tightening the metal pitch design rule increases both the line resistance and the capacitance between metal lines. Specifically, a large portion of the capacitive coupling is found in the back-end structurexe2x80x94between metal interconnects on the same level and between metal interconnects on different levels. The resulting increase in resistance-capacitance (RC) coupling undesirably increases propagation delay, increases cross-talk noise and increases power dissipation. Moreover, this capacitance is even more problematic because the metal height generally cannot be scaled down with the width due to reliability concerns.
As a result of these problems, low dielectric constant (i.e., low xcexa) materials have been widely proposed and designed for use in back-end multi-level interconnect architecture, to reduce such interlayer and intralayer capacitance. See, e.g., MRS Symposium Proceedings on Low Dielectric Constant Materials, Vols, 381, 443, 476, 511, 1995-1998; MRS Bulletin on Low Dielectric Constant Materials, Vol. 22 (1997); P. Singer, xe2x80x9cLow xcexa dielectrics: the search continues,xe2x80x9d Semiconductor International, 88 (May 1996); L. Peters, xe2x80x9cPursuing the perfect low-xcexa dielectric,xe2x80x9d Semiconductor International, 64 (September 1998). These back-end low xcexa materials have been useful in reducing undesired capacitance, but improved materials and techniques for improving the properties of shrinking devices are continually desired.
It has been discovered that, in addition to the capacitive coupling arising from the back-end structure, there is substantial capacitive coupling in the front-end structure of semiconductor devices. By providing low xcexa material capable of withstanding the harsher requirements of front-end fabrication, significant performance enhancement is attained. (The front-end structure, as known in the art, is the structure from and including the device substrate up to the first metal interconnect level (metal-1); the back-end structure is the structure including the first metal interconnect layer and above).
A typical semiconductor device according to the invention, reflected in FIG. 1, includes a substrate 12, an isolation structure in the substrate (e.g., shallow trench isolation 10), an active device structure (e.g., a transistor structure 14, 16, 18, 19, 20), a dielectric layer 26 over the active device structure, and a metal interconnect layer 28 over the dielectric layer (metal-1 level). At least one of the isolation structure 10 and the dielectric layer 26xe2x80x94which are dielectric material components in the front-end structurexe2x80x94comprise a material exhibiting a dielectric constant less than 3.5. This relatively low dielectric constant provides improved properties in the overall device by reducing capacitive coupling in the front-end.
It is not possible, however, to simply use low xcexa materials designed for a back-end structure. Low xcexa materials suitable for integration in the front-end structure must meet a different set of physical and chemical requirements. In particular, the thermal stability requirement for front-end low xcexa materials is much higher, typically at least 700xc2x0 C., and as high as 1000xc2x0 C. By contrast, typical back-end low xcexa materials such as organic or inorganic polymers generally are designed to endure only relatively low temperatures, e.g., up to 425xc2x0 C., and will not withstand front-end processing temperatures. In one embodiment of the invention, therefore, a high thermal stability porous silica is used to provide a dielectric constant less than 3.5, advantageously less than 3.0, in the front-end structure of semiconductor devices. The silica is capable of exhibiting a thermal stability of at least 700xc2x0 C., optionally at least 1000xc2x0 C. (Thermal stability indicates less than 5 wt.% loss at the noted temperature.)